This description relates to computing in parallel processing environments.
FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits) are two exemplary approaches for implementing customized logic circuits. Costs associated with ASICs include verification, physical design, timing closure, and non-recurring costs. Unlike an ASIC, an FPGA is reprogrammable in that it can be reconfigured for each application and changed even after the design has been shipped to customers, much like software can be updated. However, FPGAs are typically more expensive than an ASIC. FPGAs typically consume more power and lower performance compared to an ASIC.
Multicore systems (e.g., tiled processors) use parallel processing to achieve some features of both ASICs and FPGAs. For example, some multicore systems are power efficient like an ASIC because they use custom logic for some functions, and reconfigurable like FPGAs because they are programmable in software.
PCI Express® or PCIe is a known high-speed serial computer expansion bus standard. Modern multicore core systems on a chip (SOC) that implement high rate PCIe root complex, often have multiple downstream ports and internally embed PCIe switch functionality. PCI Express lanes of a wide port (e.g. 16 full duplex lanes) can be bifurcated into multiple narrower ports (e.g., 8, downstream ports of two full duplex lanes) that can be dedicated channels for various devices in a system. PCIe base address range definitions (BAR's) are programmed and used for PCIe controller address mapping.
Coherent mesh interconnections are used for many-core scalable platforms. Routing packets in such mesh interconnection use routers of neighboring tiles and a routing function to send data from a source tile coordinate to a destination tile coordinate, or to an edge of a mesh array. Transactions running to IO peripherals traverse the mesh interconnect towards a protocol translation block that is located outside of the mesh array. In the protocol translation block, coherent bus transactions are converted by a PCIe controller to PCI transaction layer packets (TLPs).